Senior Mask Layout Design Engineer

Job Description

NVIDIA is seeking a Senior Mask Layout Design Engineer to work on high-speed mixed-signal circuit designs using innovative sub-micron CMOS technologies.

Requirements

• Hold a BSEE or equivalent experience
• 8+ years of relevant mask design / layout experience
• Tape-out experience with FinFET technology
• Experience with TSMC N5/N4/N3 is preferred
• Deep understanding of analog circuit layout concepts in submicron CMOS technologies
• Experience with Cadence custom circuit design tools
• Ability to work optimally in a team
• Proficiency in scripting languages like perl, python, skill etc.

Responsibilities

• Perform physical layout for mixed-signal functions like PLL's, high-speed I/O circuits, general I/O's, ESD structures designs
• Customize designs for integration in VLSI products
• Floor planning, custom layout, and verifying against design rules and schematics

Benefits

• Multiple relocation packages
• Two weeklong shutdowns (mid-summer and year-end) in the US (in addition to PTO)
• 8-week parental leave
• 9 Employee Resource Groups
• Annual bonus offering
• Flexible work arrangements
• Up to 6% 401K matching