SOC Verification Engineer

Job Description

Join Apple's wireless silicon development team as a SOC Verification Engineer responsible for pre-silicon RTL verification of block and top-level SOC.

Requirements

• BS with 3+ years relevant experience
• Expertise in HVL and HDL (System Verilog, Verilog)
• Advanced knowledge of HVL methodology (UVM/OVM/VMM)
• Solid verification skills in problem-solving, constrained random testing, and debugging
• Solid understanding of reusable verification framework
• Knowledge of digital logic design, chip architecture, and microarchitecture
• Great teammate with excellent communication skills and the desire to take on diverse challenges

Responsibilities

• Understand details of different types of architecture and low power architecture
• Create detailed verification plan from specification
• Develop reusable block/IP level testbench
• Generate directed and constrained random tests
• Create/analyze coverage model and enhance testbench/test
• Build automated flows for block and chip level verification
• Debug failures, manage bug tracking, and close coverage
• Hold detailed verification reviews and set standard for coding quality
• Work closely with team members to improve methodology and flow