Design Verification Engineer

Job Description

Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple’s premier SOCs. Joining SOC DV allows you to focus deeply on one main IP or expand your breadth as you work on a collection of subsystems.

Requirements

• BS + 3 years relevant industry experience
• Skilled in digital verification processes like constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy
• Knowledge of SystemVerilog, digital simulation, debug, computer architecture, and digital design fundamentals
• SW programming skills with knowledge of data structures and algorithms
• Experience with Python, Perl, or similar scripting language
• Knowledge of verification methodologies like UVM
• Experience with C/C++, assembly is a plus
• Excellent interpersonal skills

Responsibilities

• Ensure quality of SOC, IP, or subsystem by reviewing design and architecture specifications
• Develop test plans, tests & coverage plans, define verification methodology & testbenches
• Collaborate with design, architecture, and software teams to understand use cases and drive test cases