Design Verification Engineer

Job Description

Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple’s premier SOCs. Joining SOC DV allows you to focus deeply on one main IP or expand your breadth as you work on a collection of subsystems.

Requirements

• Minimum of BS + 10 years relevant industry experience
• Skilled in digital verification processes
• Knowledge of SystemVerilog, computer architecture, and digital design fundamentals
• Experience with Python, Perl, or similar scripting language
• Ability to work independently and deliver project goals
• Knowledge of verification methodologies like UVM
• Excellent interpersonal and communication skills

Responsibilities

• Reviewing design and architecture specifications
• Developing test plans, tests & coverage plans
• Defining verification methodology & testbenches
• Collaborating with design, architecture, and software teams
• Understanding functional & performance goals of the design
• Driving test cases based on use cases and corner conditions