Design Verification Engineer

Job Description

Apple is seeking an outstandingly hardworking design verification engineer to ensure bug-free first silicon for IP designs.

Requirements

• BS degree in technical subject area with minimum 10 years of proven experience
• Solid knowledge of OOP, SystemVerilog, and UVM
• Experience with verification methodologies and tools such as simulators, waveform viewers
• Experience with power-aware (UPF) or similar verification methodology
• Excellent knowledge of one of the scripting languages such as Python, Perl, TCL

Responsibilities

• Establishing DV methodology and test-plan development
• Verification environment development including stimulus and checkers
• Developing verification plans for all features under your care
• Executing verification plans, including design bring-up and DV environment bring-up
• Developing block, IP, and SoC level test-benches