Design Verification Engineer

Job Description

Apple is looking for a design verification engineer to ensure bug-free first silicon for part of the SoC / IP, develop test and coverage plans, and execute verification plans.

Requirements

• BS degree in technical subject area with minimum 10 years of proven experience
• Solid knowledge of OOP, SystemVerilog, and UVM
• Relevant experience with verification methodologies and tools such as simulators, waveform viewers
• Experience with power-aware (UPF) or similar verification methodology
• Excellent knowledge of one of the scripting languages such as Python, Perl, TCL
• Experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required

Responsibilities

• Establishing DV methodology
• Test-plan development
• Verification environment development including stimulus and checkers
• Test-writing, debug, coverage, sign-off for RTL freeze and tape-out
• Developing detailed test and coverage plans based on the micro-architecture
• Developing verification methodology suitable for the IP
• Developing verification environment components like stimulus, checkers, assertions, trackers, coverage
• Developing verification plans for all features under your care
• Executing verification plans, design bring-up, DV environment bring-up, regression enabling features, and debug of test failures
• Developing block, IP, and SoC level test-benches
• Tracking and reporting DV progress using various metrics including bugs and coverage