Design Verification Engineer

Job Description

Apple is seeking a design verification engineer to ensure bug-free first silicon for IP designs.

Requirements

• BS degree in technical subject area with minimum 10 years of proven experience
• Solid knowledge of OOP, SystemVerilog, and UVM
• Relevant experience with verification methodologies and tools such as simulators, waveform viewers
• Experience with power-aware (UPF) or similar verification methodology
• Excellent knowledge of one of the scripting languages such as Python, Perl, TCL
• Experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus
• Knowledge of formal verification methodology is a plus

Responsibilities

• Establish DV methodology, test-plan development, verification environment development including stimulus and checkers
• Develop detailed test and coverage plans based on the micro-architecture
• Develop verification methodology suitable for the IP, ensuring a scalable and portable environment
• Develop verification environment, including components such as stimulus, checkers, assertions, trackers, coverage
• Develop verification plans for all features under your care, execute verification plans, debug test failures
• Develop block, IP and SoC level test-benches, track and report DV progress using metrics including bugs and coverage