Design Verification Engineer

Job Description

This role is for a design verification engineer at Apple responsible for ensuring bug-free first silicon for IP designs.

Requirements

• BS degree in technical subject area with minimum 10 years of proven experience
• Solid knowledge of OOP, SystemVerilog, and UVM
• Relevant experience with verification methodologies and tools such as simulators, waveform viewers
• Experience with power-aware (UPF) or similar verification methodology
• Excellent knowledge of one of the scripting languages such as Python, Perl, TCL
• Experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus
• Knowledge of formal verification methodology is a plus

Responsibilities

• Establishing DV methodology and test-plan development
• Developing verification environment including stimulus and checkers
• Developing verification plans for all features, executing verification plans, and debugging test failures
• Tracking and reporting DV progress using metrics like bugs and coverage