Design Verification Engineer

Job Description

This role is for a digital-focused DV engineer responsible for ensuring bug-free first silicon for part of the SoC / IP, including developing verification methodology and environment.

Requirements

• Bachelor of Science degree with meaningful experience or internships
• Deep knowledge of SystemVerilog and UVM
• Proven experience with verification methodologies and tools such as simulators and waveform viewers
• Experience with serial protocols like PCIe or USB, and parallel protocols like DDR
• Knowledge of scripting languages such as Python, Perl, TCL

Responsibilities

• Establishing DV methodology and test-plan development
• Developing verification environment including stimulus, checkers, assertions, trackers, coverage
• Developing verification plans, executing verification plans, and debugging test failures
• Developing block, IP, and SoC level test-benches
• Tracking and reporting DV progress using metrics like bugs and coverage