CPU Cache Microarchitect/RTL Engineer

Job Description

Apple is seeking an experienced technical leader to drive CPU multi-level cache subsystem architecture and RTL development for multi-processor systems.

Requirements

• Minimum BS and 10+ years of relevant industry experience
• Knowledge of microprocessor architecture
• Knowledge of Verilog and/or VHDL
• Experience with simulators and waveform debugging tools
• Knowledge of logic design principles along with timing and power implications

Responsibilities

• Micro-architecture development and specification
• RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals
• Verification support for the verification team
• Performance exploration and correlation
• Design delivery