Silicon Validation Engineer

Job Description

NVIDIA Silicon Solutions Group is seeking a versatile engineer to be part of the HW ArchDev team, responsible for silicon and system-level feature development, cost-benefit analysis, system integration solutions, and system POR alignment.

Requirements

• BS or MS degree in EE/CE or equivalent experience
• Effective in a collaborative environment
• 8+ years of experience in developing end-to-end silicon validation and stress testing, PVT methodologies for next-generation silicon, and deep understanding of GPU/SOC system-level architecture

Responsibilities

• Develop new end-to-end methodologies, processes, and workflows targeting system-level silicon stress, concurrency, and PVT coverage
• Lead debug efforts from the HW side to root cause feature sequences bugs, silicon bugs, and sophisticated system-level issues
• Bringup new flows, tests, and PVT solutions
• Apply insights from bring-up execution and post-action reviews to continually improve coverage

Benefits

• Multiple relocation packages
• Two weeklong shutdowns (mid-summer and year-end) in the US (in addition to PTO)
• 8-week parental leave
• 9 Employee Resource Groups
• Annual bonus offering
• Flexible work arrangements
• Up to 6% 401K matching