Senior ASIC Timing Engineer

Job Description

NVIDIA is seeking a motivated ASIC Timing Engineer to join their dynamic and growing team.

Requirements

• BS (or equivalent experience) in Electrical or Computer Engineering with 5 years experience or MS (or equivalent experience) with 2 years experience in Timing and STA
• Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints generation and management
• Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis
• Expertise and in-depth knowledge of industry standard STA and timing convergence tools
• Knowledge of deep sub-micron process nodes and hands-on experience in modeling and converging timing in these nodes

Responsibilities

• Drive timing analysis and closure of Nvidia’s GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level
• Work with PD, DFX, Clocks, and other teams in coming up with timing closure strategy, creating timing constraints, driving timing and power convergence, as well as ECO implementation
• Apply knowledge and experience to improve timing convergence flows working with the methodology teams

Benefits

• Multiple relocation packages
• Two weeklong shutdowns (mid-summer and year-end) in the US (in addition to PTO)
• 8-week parental leave
• 9 Employee Resource Groups
• Annual bonus offering
• Flexible work arrangements
• Up to 6% 401K matching