Senior ASIC Design Verification Engineer

Job Description

NVIDIA is seeking a Senior ASIC Design Verification Engineer to drive sign-off strategies for leading GPUs and SoCs, influencing the next generation of computing technology.

Requirements

• BSEE (or equivalent) with 5+ years' experience in unit level or sub-system level verification or MS preferred in Electrical, Computer Engineering with 3+ years’ experience in unit level or sub-system level verification
• Proficiency with Object Oriented Programming, System Verilog, Verilog, UVM, SVA and Functional Coverage
• Strong skills with VCS or equivalent simulation tools like Questa
• Strong debugging and analytical skills
• Continuous improvement mentality and passionate about delivering bug-free first silicon
• Strong interpersonal skills and ability to work with on-site and remote teams
• Experience in verification using random stimulus, mixed signal and custom designed IPs solutions, behavioral real number modeling, co-simulation environments, Gate Level Simulation or Formal Equivalence domains, and scripting languages such as Perl, Tcl, Make files and automation methods/algorithms

Responsibilities

• Develop innovative IPs for hardware security, clocking, voltage regulation, and silicon correlation
• Own unit and sub-system level verification of various IPs, create functional test plans, and verify using advanced verification tools
• Build world class verification infrastructure and methodologies for custom designed IPs
• Engage in design specification development and enable system level integration by working with partner teams

Benefits

• Multiple relocation packages
• Two weeklong shutdowns (mid-summer and year-end) in the US (in addition to PTO)
• 8-week parental leave
• 9 Employee Resource Groups
• Annual bonus offering
• Flexible work arrangements
• Up to 6% 401K matching