Senior ASIC Floorplan Design Engineer

Job Description

NVIDIA is seeking a Senior ASIC Floorplan Design Engineer to design and implement leading SoC's and GPU's, influencing the future of computing.

Requirements

• Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering
• 6+ years of relevant work experience
• Deep hardware engineering background with a concentration in VLSI and/or Computer Architecture
• Experience in Verilog, System Verilog or similar HVL
• Experience with CAD and physical design methodologies, chip floorplan, power/clock distribution, packaging, P&R, and timing closure
• Strong communication and interpersonal skills
• Python, Perl, and C/C++ programming language experience

Responsibilities

• Develop and optimize floorplans during early chip development
• Collaborate with design leads to identify improvement opportunities
• Solve timing and routing congestion issues
• Build tools and improve infrastructure to optimize chip area and speed of execution

Benefits

• Multiple relocation packages
• Two weeklong shutdowns (mid-summer and year-end) in the US (in addition to PTO)
• 8-week parental leave
• 9 Employee Resource Groups
• Annual bonus offering
• Flexible work arrangements
• Up to 6% 401K matching