Senior Mask Design Engineer

Job Description

NVIDIA is seeking a Senior Mask Design Engineer to work on the physical layout design and development of next-generation custom SRAM macro-IPs.

Requirements

• Bachelor’s Degree or equivalent experience
• 5+ years' proven experience in memory macro layout
• Strong background in tight pitch related layout design
• Knowledge of the latest FinFET technology nodes and design rules
• Strong proficiency of layout tools (Cadence Virtuoso is desired)
• Knowledge of ICV layout verification tool is a plus
• Scripting skills in CSH, PERL or SKILL
• Excellent interpersonal skills and ability to work with multi-functional teams
• Excellent writing and reporting skills

Responsibilities

• Perform physical layout of SRAM and datapath circuits using Cadence tools
• Floor-planning, hierarchical layout assembly, cell sharing, and custom layout design
• Recognize different solutions in layout implementation based on area, metal utilization, and schedule
• Develop physical verification flows for new technologies - DRC and LVS
• Work closely with circuit engineers to establish layout design methodologies

Benefits

• Multiple relocation packages
• Two weeklong shutdowns (mid-summer and year-end) in the US (in addition to PTO)
• 8-week parental leave
• 9 Employee Resource Groups
• Annual bonus offering
• Flexible work arrangements
• Up to 6% 401K matching