Senior DFT Methodology Engineer

Job Description

DFX Methodology Group at NVIDIA is looking for a creative and autonomous engineer with a real passion for technology to work on groundbreaking innovations involving crafting creative solutions for cutting-edge test techniques.

Requirements

• BSEE (or equivalent experience) with 5+ years, MSEE with 3+ years, or PhD with 2+ years of experience in DFT, system architecture, or RTL design
• Understanding of fundamental DFT topics such as fault modeling, ATPG, and fault simulation
• Experience in Silicon debug and bring-up on the ATE or SLT platforms
• Excellent understanding of MBIST and IOBIST fundamentals
• Experience in architecting DFT access mechanisms in 3D stacked and dielet/chiplet based designs, and UCIe protocol
• Good understanding of RTL coding principles
• Knowledge of high-speed interface architectures such as PCIe, USB3, DDR
• Excellent analytical skills in verification and validation of logic on complex and multi-million gate designs using vendor tools
• Good exposure to multi-functional areas including RTL & clocks design, STA, place-n-route, and power
• Strong programming and scripting skills in Perl, Python, or Tcl desired
• Outstanding written and oral communication skills with the curiosity to work on rare challenges

Responsibilities

• Work on next-generation test architectures
• Implement brand-new designs in test access mechanisms, high-speed test interfaces, and in-system test architecture
• Develop and deploy In-System Test (IST) methodologies for next-generation products
• Mentor junior engineers on test designs and trade-offs including cost and quality

Benefits

• Multiple relocation packages
• Two weeklong shutdowns (mid-summer and year-end) in the US (in addition to PTO)
• 8-week parental leave
• 9 Employee Resource Groups
• Annual bonus offering
• Flexible work arrangements
• Up to 6% 401K matching