Senior ASIC Timing Engineer

Job Description

Join NVIDIA's Advanced Technology Group as a Senior ASIC Timing Engineer to work on next-generation CMOS technology optimization and design tradeoffs.

Requirements

• BS in Electrical or Computer Engineering or equivalent experience
• 8+ years experience in Physical design/Timing
• Experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence
• Expertise in physical design, optimization, and ECO implementation
• Hands-on knowledge of industry standard Timing/STA EDA tools
• Proficiency in programming and scripting languages such as TCL and Python

Responsibilities

• Responsible for timing analysis and closure, timing environment, setting up constraints, and defining timing methodology for next-generation designs
• Work with place and route to implement around constraints, find tradeoffs between frequency and power/area/congestions/yield, etc.
• Work on all aspects of DFT/Test timing such as timing constraints, timing analysis, timing convergence, and ECO implementation

Benefits

• Multiple relocation packages
• Two weeklong shutdowns (mid-summer and year-end) in the US (in addition to PTO)
• 8-week parental leave
• 9 Employee Resource Groups
• Annual bonus offering
• Flexible work arrangements
• Up to 6% 401K matching