Senior Timing Methodology Engineer

Job Description

NVIDIA is seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and SoCs.

Requirements

• MS (or equivalent experience) in Electrical or Computer Engineering
• 3 years’ experience in ASIC Design and Timing
• Good understanding of modeling circuits for sign-off
• Expertise in coding- TCL, Python. C++ is a plus
• Familiarity with industry standard ASIC tools: PT, ICC, Redhawk, Tempus etc.

Responsibilities

• Improve and validate flows for Prime-Time, Prime-Shield and Tempus STA QoR metrics for sign-off flow and tool for high-speed designs
• Develop custom flows for validating QoR of ETM models, both of std cells and custom IPs
• Develop flows/recommendations on STA sign-off to model deep submicron physical effects aging, self-heating, thermal impact, IR drop etc.
• Collaborate with technology leads, VLSI physical design, and timing engineers to define and deploy sophisticated strategies of signing off timing in design
• Develop tools and methodologies to improve design performance, predictability, and silicon reliability beyond industry standard tools

Benefits

• Multiple relocation packages
• Two weeklong shutdowns (mid-summer and year-end) in the US (in addition to PTO)
• 8-week parental leave
• 9 Employee Resource Groups
• Annual bonus offering
• Flexible work arrangements
• Up to 6% 401K matching