Senior DFT Engineer

Job Description

NVIDIA is seeking a Design-for-Test Engineering professional to work on groundbreaking innovations in DFT architecture, verification, and post-silicon validation.

Requirements

• BSEE (or equivalent experience) with 5+ years, MSEE with 3+ years of experience, or PhD in DFT or related domains
• Demonstrated knowledge and expertise in defining scan test plans, BIST, fault modeling, ATPG, and fault simulation
• Excellent analytical skills in verification and validation of test patterns and logic on complex designs
• Experience in Silicon debug and bring-up on the ATE with knowledge of pattern formats, failure processing, and test program development
• Strong programming and scripting skills in Perl, Python, or Tcl desired

Responsibilities

• Own and work with cross-functional teams to implement state-of-the-art designs in test access mechanisms, IO BIST, memory BIST, and scan compression
• Develop and deploy DFT methodologies for next-generation products
• Mentor junior engineers on test designs and trade-offs including cost and quality

Benefits

• Multiple relocation packages
• Two weeklong shutdowns (mid-summer and year-end) in the US (in addition to PTO)
• 8-week parental leave
• 9 Employee Resource Groups
• Annual bonus offering
• Flexible work arrangements
• Up to 6% 401K matching