Low Power ASIC Engineer - New College Grad 2025

Job Description

NVIDIA is seeking a Low Power Design/Verification ASIC Engineer - New College Grad 2025 to work on energy-efficient GPU and SOC architectures.

Requirements

• BS, MS or PhD in Electrical or Computer Engineering
• Strong background in Low Power architectures or verification
• Understanding of low power design techniques such as multi VT, Clock gating, Power gating, Block Activity Power, and Dynamic Voltage-Frequency Scaling (DVFS)
• Good understanding of processor architecture and related power management design/DV techniques
• Experience with Incisive Low-Power or Synopsys VCS NLP
• Fluent in Verilog, SystemVerilog, and understanding of UVM

Responsibilities

• Work closely with Low Power Architecture, Design, and Software teams
• Architect/develop testbench, infrastructure, and testplans for power management solutions
• Bring creative ideas to improve power-aware DV methodologies
• Influence EDA vendors to enhance simulation and debug efficiencies

Benefits

• Multiple relocation packages
• Two weeklong shutdowns (mid-summer and year-end) in the US (in addition to PTO)
• 8-week parental leave
• 9 Employee Resource Groups
• Annual bonus offering
• Flexible work arrangements
• Up to 6% 401K matching