CAD Engineer - Timing for Gate-Level Flows & Methodologies

Job Description

Join the STA CAD team at Apple to develop and maintain gate-level STA flows for high-performance, power-efficient processors and SoCs.

Requirements

• BS in relevant field
• 10+ years of industry experience
• Expertise in static timing analysis tools and flows
• Advanced programming skills in Python and Tcl
• Experience with CAD flows and automation
• Familiarity with high-performance SoC designs in deep sub-micron technologies
• Deep understanding of noise, cross-talk, variation, margins, and timing models
• Knowledge of timing/SDC constraints

Responsibilities

• Develop, maintain, and enhance gate-level STA flows for Apple silicon designs
• Collaborate with design teams to address timing challenges and improve timing closure
• Drive STA methodology changes for improved efficiency/productivity and silicon timing correlation
• Develop scripts and methods for timing analysis and power reduction
• Support verification of timing constraints and best practices across design teams
• Analyze timing paths for key issues and contribute to post-silicon timing debug
• Engage with EDA vendors to incorporate new capabilities for technical problem-solving

Benefits

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.