ASIC Design Engineer - Cache Controller

Job Description

Apple is looking for a hardware design engineer to work on cache subsystems for high-performance systems on a chip (SoC), focusing on memory system development and architecture trade-offs.

Requirements

• 3+ years of full-time ASIC design experience in memory system development, RTL/micro-architecture definition, and PPA analysis
• B.S. in a relevant field

Responsibilities

• Design and develop hardware for cache subsystem in high-performance SoC
• Develop cache micro-architecture based on architecture guidelines and model analysis
• Explore architecture trade-offs in system performance, area, and power consumption
• Develop and debug RTL design of various sections in the cache subsystem
• Work on front-end netlist and area/timing analysis of the cache subsystem
• Work with physical design team on the timing closure of the cache subsystem

Benefits

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.