STA Engineer

Job Description

As an ASIC STA Engineer at Apple, you will be responsible for full chip and block level timing closure, methodology development, and working on Apple SoC chips for high-end mobile applications.

Requirements

• Bachelors Degree + 3 Years of Experience
• Strong fundamentals in Digital design
• Proficient in scripting languages (TCL and Perl)
• Familiarity with ASIC design timing concepts
• Exposure in STA tools (Primetime) is a plus
• Familiarity with front end tools and methodologies such as Synthesis, Logic equivalence checks
• Knowledge of timing corners/modes, process variations, and signal integrity related issues
• Ability to communicate optimally across all internal groups

Responsibilities

• Full chip and block level timing closure ownership
• Develop and maintain methodology and flows related to timing verification and closure
• Generation of block and full chip timing constraints
• Work closely with various multi-functional teams on resolving complex timing issues for major building blocks of complex SoCs

Benefits

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.