Senior ASIC Test Timing Engineer

Job Description

NVIDIA is seeking a motivated Senior ASIC Test Timing Engineer to join their dynamic team and work on advanced GPU, CPU, DPU, and SoC projects.

Requirements

• BS or MS in Electrical or Computer Engineering
• 5+ years of experience for BS or 2+ years of experience for MS in Timing and STA
• Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence
• Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis
• Knowledge of industry standard STA and timing convergence tools
• Experience in deep sub-micron process nodes and timing convergence in these nodes

Responsibilities

• Drive timing analysis and closure of GPUs, CPUs, DPUs, and SoCs at different levels
• Collaborate with various teams to create timing closure strategies, constraints, and drive convergence
• Improve timing convergence flows and work with methodology teams

Benefits

• Employees at NVIDIA are often offered comprehensive, day-one benefits—including medical, dental, and vision coverage with HSA support, life and disability insurance, an Employee Assistance Program, and a 401(k) with auto-enrollment. Many roles also have generous time off and holidays, donation matching (up to $10,000), and a wide menu of extras like FSAs, commuter benefits, legal and identity-theft protection, pet insurance, and wellness discounts. Optional programs can include student-loan and home-purchase support, plus family care resources and expert medical services.