CPU Cache Microarchitect/RTL Engineer

Job Description

Apple's Silicon Engineering Group is seeking a CPU RTL Architect to drive CPU multi-level cache subsystem architecture and RTL development for multi-processor systems.

Requirements

• Minimum BS and 10+ years of relevant industry experience
• Experience with microprocessor cache design or coherent system cache design
• Experience with Verilog and/or VHDL

Responsibilities

• Micro-architecture development and specification
• RTL ownership for power, performance, area, and timing goals
• Support verification team in test bench development
• Explore high-performance strategies
• Work with multi-functional engineering team for physical design implementation

Benefits

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.