Timing & Synthesis Engineer

Job Description

Join Apple's wireless silicon development team to work on developing Wireless SoCs with custom hardware accelerators and multiple processor sub-systems.

Requirements

• Bachelors degree and 3+ years of relevant industry experience
• Timing constraint (SDC) creation at partition and chip level
• Logic synthesis execution (verilog RTL to netlist)

Responsibilities

• Full chip and block-level timing constraint creation, review and closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation)
• Execute low power physical synthesis techniques, deploying knowledge of UPF and power intent verification
• Deploy and enhance methodology and flows related to timing constraint verification and timing closure
• Generation of consistent block and full chip timing constraints
• Support digital chip integration work and flows (e.g. CDC)
• Collaborate with Chip Architecture, Design Verification, Physical Design, DFT, and power teams to achieve first time Silicon success
• Generally bridge between the RTL front end and place & route worlds

Benefits

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.