Power UPF Methodology Engineer

Job Description

Join our silicon design group as a Power UPF Engineer and contribute to state-of-the-art ASIC design by driving transistor level power ERC sign-off and power intent-UPF implementation & verification on mobile SOCs.

Requirements

• Bachelor's degree in relevant field
• Minimum of 3 years of relevant industry experience
• Experience in ASIC design methodology with emphasis on power definition
• Familiarity with ASIC design flows and custom IP design flows
• Knowledge of scripting languages like Tcl, Perl, and Python
• Familiarity with power analysis and optimization methods
• Strong communication skills

Responsibilities

• Develop and support transistor level power ERC sign-off for digital and mixed signal designs
• Drive power ERC sign-off at full-chip level
• Drive UPF implementation and verification for mobile SOCs
• Enhance power sign-off flow and methodology for next-generation mobile products
• Define and develop power ERC framework for new projects
• Collaborate with CAD and physical design verification team for debugging power ERC issues

Benefits

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.