Senior ASIC Timing Engineer

Job Description

NVIDIA is looking for a motivated ASIC Timing Engineer to join their dynamic and growing team, focusing on timing analysis and closure of GPUs, CPUs, DPUs, and SoCs.

Requirements

• BS or equivalent experience in Electrical or Computer Engineering with 5 years experience, or MS with 2 years experience in Timing and STA
• Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints generation and management
• Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis
• Expertise and in-depth knowledge of industry standard STA and timing convergence tools
• Knowledge of deep sub-micron process nodes and hands-on experience in modeling and converging timing in these nodes

Responsibilities

• Drive timing analysis and closure of Nvidia’s GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level
• Work with PD, DFX, Clocks, and other teams in coming up with timing closure strategy, creating timing constraints, driving timing and power convergence, as well as ECO implementation
• Apply knowledge and experience to improve timing convergence flows working with the methodology teams

Benefits

• Employees at NVIDIA are often offered comprehensive, day-one benefits—including medical, dental, and vision coverage with HSA support, life and disability insurance, an Employee Assistance Program, and a 401(k) with auto-enrollment. Many roles also have generous time off and holidays, donation matching (up to $10,000), and a wide menu of extras like FSAs, commuter benefits, legal and identity-theft protection, pet insurance, and wellness discounts. Optional programs can include student-loan and home-purchase support, plus family care resources and expert medical services.