CMOS Device and PPA Engineer, Silicon

Job Description

Be part of a team at Google developing custom silicon solutions for direct-to-consumer products, contributing to innovation in hardware experiences.

Requirements

• Bachelor's degree in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, related degree, or equivalent practical experience
• 10 years of experience in standard cell or block-level characterization and Power, Performance, and Area (PPA) evaluation
• Experience in CMOS technology, device characterization, process integration, SPICE simulation, and physical design flows (e.g., Cadence or Synopsys)
• Experience with data analysis tools (e.g., JMP, or other spreadsheet software)

Responsibilities

• Conduct in-depth Power, Performance, and Area (PPA) evaluations at the standard cell and block levels to guide technology and design decisions
• Drive Design Technology Co-Optimization (DTCO) at the standard cell and block level to achieve optimal PPA characteristics
• Leverage physical design flows and CAD tools to perform detailed analysis, identify PPA trade-offs, and propose solutions
• Develop and maintain benchmarking infrastructure and methodologies for PPA evaluation of IP and memory blocks
• Collaborate with process, circuit, and physical design teams to co-optimize technology and design for PPA

Benefits

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.