Senior Timing Methodology Engineer

Job Description

NVIDIA is seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and SoCs.

Requirements

• MS (or equivalent experience) in Electrical or Computer Engineering with 3 years’ experience in ASIC Design and Timing
• Good understanding of modeling circuits for sign-off
• Expertise in coding- TCL, Python. C++ is a plus
• Hands-on experience in advanced CMOS technologies, design with FinFET technology 5nm/3nm/2nm and beyond
• Strong communications skill and good standout colleague

Responsibilities

• Improve and validate flows for Prime-Time, Prime-Shield and Tempus STA QoR metrics for sign-off flow
• Develop custom flows for validating QoR of ETM models, both of std cells and custom IPs
• Collaborate with technology leads, VLSI physical design, and timing engineers to define and deploy sophisticated strategies of signing off timing in design
• Develop tools and methodologies to improve design performance, predictability, and silicon reliability beyond industry standard tools

Benefits

• Employees at NVIDIA are often offered comprehensive, day-one benefits—including medical, dental, and vision coverage with HSA support, life and disability insurance, an Employee Assistance Program, and a 401(k) with auto-enrollment. Many roles also have generous time off and holidays, donation matching (up to $10,000), and a wide menu of extras like FSAs, commuter benefits, legal and identity-theft protection, pet insurance, and wellness discounts. Optional programs can include student-loan and home-purchase support, plus family care resources and expert medical services.