PLL/Clocking Design Engineer

Job Description

Join Apple's Analog-Mixed/Signal group to develop cutting-edge frequency synthesizers for various applications and contribute to Apple's innovation and market leadership.

Requirements

• BSEE with at least 10 years of relevant experience
• Demonstrated proficiency in PLL/FLL and frequency synthesis architecture and circuit design
• Deep understanding of clocking fundamentals, phase noise, and jitter analysis
• Skilled in developing System Verilog models and performing behavioral simulations
• Exceptional attention to detail and problem-solving skills
• History of innovation, self-directed learning, and teamwork capabilities

Responsibilities

• Develop cutting-edge frequency synthesizers for Compute, SoC, SerDes, and Cellular technologies
• Contribute to maintaining Apple's leadership in innovation and market presence
• Explore new architectural performance through simulations and modeling
• Collaborate with a team of exceptional individuals to solve complex problems

Benefits

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.