Physical Synthesis CAD Engineer

Job Description

Join the Silicon Technologies group at Apple to help design and manufacture next-generation, high-performance processors and system-on-chips.

Requirements

• Minimum requirement of BS
• Knowledge of Logic design fundamentals
• Experience with Synthesizable System Verilog RTL
• Knowledge or experience with industry standard Logic Synthesis tools like Fusion Compiler or Genus
• Exposure to static timing analysis and logic equivalence tools
• Experience with writing synthesizable RTL code
• Proficiency with TCL, Python or Perl scripting languages strongly preferred

Responsibilities

• Develop and improve flows for Physical Synthesis and DFT Implementation
• Support multiple design teams and work with cross functional teams to solve key physical synthesis challenges
• Collaborate with other flows like Logic Equivalence, Static Timing Analysis and Low Power (UPF) Implementation
• Work with tool vendors to resolve tool/flow issues

Benefits

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.