CPU Cache RTL Engineer

Job Description

Apple is looking for a CPU Cache RTL Engineer to drive CPU multi-level cache subsystem architecture and RTL development for multi-processor systems.

Requirements

• Minimum BS in a related field
• Experience with Verilog or VHDL

Responsibilities

• Participate in micro-architecture development and specification
• Own RTL development to target power, performance, area, and timing goals
• Support verification team in test bench development and formal methods
• Explore performance strategies and work with performance verification team
• Work with multi-functional engineering team to implement and verify physical design

Benefits

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.