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Physical Design Engineer, 3D Technology, PhD, University Graduate

Google
Sunnyvale, CA Full-time 12/24/2025 $132k - $189k per year
PhD Entry-Level
Approval 99%Total filings 5,616New hires 2,898
👑 Elite Sponsor
FY 2025

Job Description

This role involves working as a Physical Design Engineer in 3D Technology, focusing on developing custom silicon solutions for AI/ML hardware acceleration. You will collaborate with various teams to optimize digital designs and drive innovations in 3D technology physical design methodologies.

Requirements

  • PhD degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • Academic, educational, internship, or project experience with physical design and 3D integration technologies such as 3D-IC, 2.5D, chip stacking, vertical stacking, integrity, or Through-Silicon Vias (TSV).
  • Experience with running industry standard tools for chip design (e.g., from Synopsys, Cadence, or Siemens EDA).
  • Experience with advanced finfet and gate-all-around technology nodes, and enabling physical design flows in these nodes.
  • Experience in delivering optimized digital place-and-route blocks leading to test chip or product tapeouts.
  • Experience with programming/scripting (TCL, Python, or Perl).
  • Expertise with Power, Performance, and Area (PPA) design trade-offs and optimizations in physical design spaces.
  • Understanding of standard cells, SRAMs, power, noise, and IR analysis.
  • Excellent presentation and communication skills.

Responsibilities

  • Drive development of a leading edge 3D technology platform for custom, high performance ASIC’s and SoC’s, from design through manufacturing, packaging, and test.
  • Optimize digital blocks for performance, power, area, and reliability using physical design and circuit techniques.
  • Define optimal methodologies by investigating performance, power, and area across different technology nodes and implementation techniques.
  • Work with our physical design, technology, circuits, and architecture teams and IP partners in advanced Complementary Metal-Oxide-Semiconductor (CMOS) nodes.
  • Design and build custom circuits at the transistor and gate levels to support physical design and floorplan optimization.

Benefits

  • Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.