Job Description

In this role, you will design and develop clocking infrastructures for Google's next-generation Tensor Processing Units (TPUs), focusing on advanced clock control mechanisms. You will collaborate with cross-functional teams to ensure optimal performance and power management in AI/ML hardware acceleration.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
2 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development.
Experience with digital clock control circuits, including clock dividers, glitch-free muxes, and clock gating.
Experience in SystemVerilog for creating microarchitecture specifications and synthesizable RTL.
Experience with design quality tools, specifically for Clock Domain Crossing (CDC), linting, and static timing analysis.
Experience using Python, Tcl, or Perl for automating design tasks and data analysis.

Responsibilities

Define specifications and develop SystemVerilog for advanced clocking features, including FLL/PLL controllers, dividers, and glitch-free multiplexer logic.
Design and optimize dynamic power-saving mechanisms such as clock skipping (pulse swallowing), frequency scaling sequences, and fine-grained clock gating.
Partner with architecture teams to evaluate clock-tree impacts and implement infrastructure supporting various SoC power states and performance levels.
Collaborate with Physical Design teams to manage skew, jitter, and multi-cycle paths, ensuring the CCU meets stringent timing and area goals.
Work with Design Verification and Silicon bring-up teams to create test plans for clocking corner cases and root-cause issues in simulation and emulation.

Benefits

Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.