Job Description

This role involves shaping the future of AI/ML hardware acceleration by developing cutting-edge TPU technology for Google's demanding applications. The position requires collaboration with cross-functional teams to deliver advanced custom silicon solutions and contribute to the innovation behind products used by millions worldwide.

Requirements

Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience.
8 years of experience in analog mixed signal or high-speed IO development.
Experience defining and taking to HVM leading edge mixed-signal or high-speed IO designs.
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on wireline silicon architecture and design (preferred).
Experience working on high-performance, data-center class IP, from concept through high-volume deployment (preferred).
Experience and technical innovation in mixed-signal and high-speed IO solutions (preferred).

Responsibilities

Design of high-speed analog/digital circuits (e.g., ADC, DAC, PLL, CDR, DSP), including optimizing for Power, Performance, and Area (PPA).
Model and simulate channel behavior (S-parameters), signal integrity, and jitter using tools like MATLAB.
Bring up new silicon, characterize performance, and test for electrical compliance in lab environments.
Work with packaging, board design, and firmware teams to ensure seamless integration into System-on-Chips (SoCs).
Adhere to standards like IEEE or OIF for high-speed protocols and optimize power consumption.

Benefits

Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.