Job Description

In this role, you will shape the future of AI/ML hardware acceleration by driving cutting-edge TPU technology. You will collaborate with various teams to deliver optimized custom circuits and SRAMs, focusing on advanced ASICs and SoCs, while managing product performance, power, and area.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
5 years of experience in Circuit Design, Physical Design (RTL-to-GDS), or Technology Development, including advanced nodes (e.g., 7nm or below).
Experience with concurrent optimization across custom circuit/IP and physical design, including Place and Route (PNR) and Static Timing Analysis (STA).
Experience with SPICE and transistor level design in advanced nodes.
Experience in CMOS device physics, finfet/GAA/nanosheet architectures, and layout parasitics.
Experience in scripting and automation using Tcl and Python (or Perl).

Responsibilities

Evaluate, analyze, implement, and integrate SRAMs, other memories (such as multiport register files), and custom circuits.
Drive proper IP integration and margins with the physical design team.
Work with our foundry and IP partners plus our technology, physical design, and architecture teams in advanced CMOS nodes to optimize our products for Power Purchase Agreement (PPA), schedule, and reliability.
Drive and support test chip design, execution, and validation of critical circuit IPs.
Design and build custom circuits at the transistor and gate levels to support physical design and power-performance-area optimization.
Drive development of a leading edge technology platform for custom, high performance ASIC’s and SoC’s, from design through manufacturing, packaging, and test.

Benefits

Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.