Design Engineer – AI SoC Development
Intel Santa Clara, CA Full-time 3/24/2026 $164.5k - $232.2k per year
Undergraduate with 5+ Years of Experience
Approval 96.6%•Total filings 2,117•New hires 632•
💎 Strong Sponsor
•FY 2025Job Description
Join Intel's AI SoC organization as an RTL Design Engineer, where you'll develop logic design and RTL coding for SoC designs. This role involves integrating IP blocks, defining architecture features, and collaborating with verification teams to ensure design integrity and performance.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science
- 4+ years of experience in RTL design and implementation for ASIC/SoC development
- Proficiency in Verilog/System Verilog for RTL coding and design
- Experience with synthesis tools and timing closure methodologies
Responsibilities
- Contribute to evaluation of architectural trade-offs considering features, performance, and system constraints
- Implement RTL in Verilog/System Verilog based on defined micro-architecture
- Integrate IP blocks at top level and ensure synthesis- and timing-clean design
- Work closely with verification teams to achieve full coverage and robust validation
- Develop timing constraints for IP blocks and assist physical design teams with synthesis, timing closure, and formal equivalence checks
- Support silicon bring-up and post-silicon validation activities, including debug and performance analysis
- Collaborate with senior engineers to adopt best practices and improve design methodologies
- Drive quality assurance compliance for smooth IP/SoC handoff
- Work with IP providers to integrate and validate IPs at the SoC level
Benefits
- Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.
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