Tesla's AI Hardware team is seeking a highly motivated ASIC RTL Design Engineer specializing in custom AI accelerators. The role focuses on designing high-performance, power-efficient RTL for math-intensive components that support AI training and inference systems, emphasizing expertise in tensor operations and optimized data paths.

• Degree in Electrical Engineering, Computer Engineering, or related field, or equivalent experience
• 10+ years across ATPG, ATE test development, and DFT timing
• Expert-level Tessent proficiency — TestKompress and MemoryBIST
• Deep knowledge of fault models: stuck-at, transition, path delay, cell-aware, and SDD
• ATE test program development and OSAT deployment experience
• SDC constraint development for DFT test modes; timing closure using Tempus
• Ability to use agentic AI flows to automate ATPG and ATE test workflows

• Generate production-quality ATPG patterns using Tessent for various fault models
• Achieve and exceed coverage targets while minimizing pattern count for ATE test time
• Debug low coverage areas and ATPG abort conditions
• Perform gate-level pattern simulation to validate pattern integrity
• Support hierarchical and flat ATPG methodologies for multi-million gate SoC designs
• Architect and develop comprehensive ATE test programs
• Own NPI silicon bring-up for structural tests and debug failures
• Deploy and optimize test programs at OSATs for yield, quality, reliability, and cost
• Develop custom test methods for product-specific requirements

• Employees at Tesla are often offered day-one coverage with multiple medical options (some at $0 paycheck cost), dental/vision, company HSA contributions, a 401(k) match, and equity programs. Most roles also include paid time off and holidays, family-building support, employee assistance, commuter and childcare benefits, and access to discounts and wellness programs.