As an ASIC STA Engineer at Apple, you will be integral to the chip design process, focusing on timing analysis and closure for advanced SoCs. You will work closely with designers to generate timing constraints and resolve complex timing issues. This role involves ensuring that Apple products meet stringent timing requirements across various conditions. You will contribute to the development of industry-leading 5G modem platforms and help innovate new cellular technologies.

• Bachelor's degree in Electrical Engineering or Computer Science is required.
• Knowledge in ASIC timing constraints generation and timing closure.
• Good knowledge in STA tools such as Primetime and methodologies for timing closure.
• Proficient in scripting languages including Tcl and Perl/Python.
• MS degree is preferred.

• Own timing sign-off for block and chip level including custom timing checks.
• Generate block and full chip timing constraints.
• Collaborate with multi-functional teams to resolve sophisticated timing issues.
• Work on timing/SDC constraints generation and management.
• Understand and implement improvements to existing methodologies and flows.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.