As a Design Verification Engineer at Apple, you will be integral to the verification efforts of next-generation cellular systems. You will work on innovative baseband modems and RF link controllers, ensuring their quality and reliability. The role involves crafting reusable UVM verification environments and developing comprehensive test cases. You will collaborate with multi-functional teams to deliver cellular systems that enhance customer experiences globally.

• BS degree and a minimum of 10 years relevant industry experience
• Strong knowledge of System Verilog and UVM
• Skilled in System C, C/C++, Python/perl
• Experience with developing Python-based automation solutions
• Master of Science degree in Electrical Engineering or Computer Science
• Knowledge of 4G/5G cellular physical layer operation (3GPP)
• Experience in using LLMs and MCPs

• Ensure the quality and reliability of next-generation cellular systems
• Craft highly reusable UVM verification environments
• Develop comprehensive coverage-driven and directed test cases
• Drive methodology innovation by deploying sophisticated tools and techniques
• Collaborate with product development teams across Apple
• Address verification challenges in complex, high-performance cellular systems

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.