The RTL Design Engineer for Machine Learning Accelerators at Google will focus on shaping the future of AI/ML hardware acceleration. This role involves working with cutting-edge TPU technology that powers Google's AI/ML applications. The engineer will be part of a team dedicated to developing custom silicon solutions and verifying complex digital designs, particularly in TPU architecture. The position offers an opportunity to contribute to innovations that impact millions of users worldwide.

• Bachelor's degree in electrical engineering, computer engineering, computer science, or a related field, or equivalent practical experience.
• 4 years of experience with custom silicon design, such as SoCs or ASICs.
• Experience with RTL design using Verilog or SystemVerilog.
• Master's degree or PhD in electrical engineering, computer engineering, or computer science is preferred.
• Experience with a scripting language, such as Python or Perl.

• Understand the overall application of the chip and propose improvements in design.
• Design and document one or more blocks of an ASIC, including functionality and timing.
• Collaborate with software teams on functionality, interfaces, and documentation.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.