The ASIC Design Verification Engineer role at Google focuses on shaping the future of AI/ML hardware acceleration, specifically through the development of Tensor Processing Unit (TPU) technology. The position is part of the AI and Infrastructure team, which is dedicated to delivering innovative computing solutions at scale. The engineer will leverage their design and verification expertise to verify complex digital designs, particularly in TPU architecture. This role involves collaboration with design engineers and the use of advanced verification methodologies to ensure the functionality and reliability of designs.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with design verification.
• Experience with SystemVerilog/Verilog.
• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science is preferred.
• 6 years of experience with silicon design verification is preferred.
• Experience with scripting languages such as Python or Perl is preferred.

• Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers.
• Create and enhance constrained-random verification environments using SystemVerilog and UVM.
• Identify and write coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to ensure functionally correct design blocks.
• Close coverage measures to identify verification holes and demonstrate progress towards tape-out.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.