The Timing Engineer will be part of Apple's wireless silicon development team, focusing on the design and implementation of Wireless SoCs with custom hardware accelerators. This role emphasizes collaboration with SoC architects and IP developers to achieve power, performance, and area goals. The engineer will enhance processes and tools for designing complex SoCs while ensuring high-quality delivery through targeted checks. This position is critical in the ASIC creation effort, impacting the launch of leading-edge products.

• Bachelor's degree and 3+ years of relevant industry experience.
• Strong knowledge of the entire ASIC design process, from RTL through synthesis, static timing analysis, and place & route.
• Expertise in STA tools and flow.
• Knowledge of timing corners, operating modes, process variation, and signal integrity-related issues.
• Skilled in scripting languages such as TCL, PERL, and Python.
• Proficient in RTL Verilog/VHDL.

• Create timing constraints (SDC) at partition and chip level.
• Execute logic synthesis from Verilog RTL to netlist.
• Collaborate with multi-disciplinary groups to ensure timely and high-quality design delivery.
• Interface with all disciplines in the ASIC creation effort.
• Close end-to-end logic equivalence with functional ECOs in the mix.
• Familiarize with DFT approaches and constraints.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.