The RFIC Layout Engineer will focus on advancing RF analog circuit integration for wireless transceivers. This role involves addressing layout challenges and collaborating with skilled RFIC design and layout teams. The engineer will work on detailed custom blocks, including floorplanning, placement, routing, and verification for high-frequency RF circuits. Continuous improvement of products and methodologies is essential to enhance user experiences worldwide.

• BS degree with 10+ years of industry experience
• Deep knowledge of sub-micron CMOS technologies, including 16nm and 7nm
• Proficiency with FinFET structures, guard-rings, deep N-wells, and PN junctions
• Familiarity with sophisticated process effects such as LOD, WPE, and DFM
• Understanding of trade-offs involving matching, parasitic effects, and high-frequency routing
• Experience in sophisticated DRC, ERC, LVS verification, and debugging
• Prior experience in crafting custom layouts for RF high-frequency circuits is a plus

• Lay out detailed custom blocks for high-frequency RF circuits
• Verify and refine layouts through simulation to meet design requirements
• Diagnose verification issues using Cadence and Calibre
• Collaborate with engineering design and layout teams to understand design concepts
• Propose solutions to streamline layout tasks and finalize methodologies

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.