The Standard Cell Designer role is part of the Digital Design Engineering group, focusing on creating innovative solutions for processor design using deep submicron technologies. This position involves working closely with custom digital circuits and library development to enhance product delivery. The designer will engage in transistor level circuit design, modeling, and performance analysis while collaborating with various teams. This role is critical in driving library architecture optimization and improving overall design performance.

• BS in a relevant field of study and a minimum of 3 years of relevant industry experience.
• Strong understanding of CMOS device characteristics and design rules.
• Strong understanding of digital circuits and optimization for better performance, power, and area (PPA).
• Good layout design knowledge and parasitic optimization in various types of layouts.
• Hands-on experience running SPICE simulations and high sigma variation analysis.
• Experience in circuit design of high-performance flip flops, level shifters, retention flops, and other complex circuits is a plus.
• Experience in RTL2GDSII flow and/or Static Timing Analysis (STA) is a plus.
• Knowledge of deep submicron process issues and FinFET technologies is a plus.
• Understanding of timing characterization and modeling of standard cell circuits is a plus.
• Strong proficiency in scripting languages like Perl, Python, and Tcl.
• Great teammate with good communication and analytical skills.
• MSEE preferred.

• Work on library architecture discussion and optimization efforts to improve overall library PPA.
• Drive layout optimization efforts by identifying and reducing parasitics to push circuit PPA.
• Work on library PPA for different technology, architecture, and PDK releases.
• Develop standard cell circuits that push design PPA.
• Work on PNR block to validate the IP in test chips and benchmark new tech/PDK libraries.
• Work on library characterization for timing, power, variation, and other factors for all libraries.
• Engage with CPU, SOC, and GPU teams on physical design requirements.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.