In this role at Apple, you will be responsible for the physical implementation of design partitions for a complex SOC. You will work closely with the logic design team to drive physical aspects early in the design cycle. Your focus will be on completing netlist to GDS2 implementation while ensuring timing, physical, and electrical verification. This position requires a commitment to innovation and collaboration to optimize design performance.

• Minimum BS and 0+ years of industry experience
• MS in Electrical/Electronics/Computer Engineering or related field
• Experience with partition level P&R implementation including floorplanning and timing closure
• Familiarity with process-related design issues including Design for Yield and Manufacturability
• Experience with large SOC designs exceeding 20M gates with frequencies over 1GHz
• Strong communication skills

• Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle
• Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals
• Perform timing, physical and electrical verification, and drive signoff closure for the partitions
• Resolve and improve design and flow issues related to physical design and drive execution
• Drive optimization of PnR partitions to achieve best Power/Performance/Area

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.