This role is for a design verification engineer at Apple, focusing on digital verification for IP designs. The engineer will work on pre-silicon verification phases, ensuring the production of fully functional first silicon. The position involves developing verification methodologies and environments, as well as executing detailed test and coverage plans. This opportunity allows for significant contributions to upcoming products that will impact millions of customers.

• Bachelor's degree in a technical subject area.
• A minimum of 3 years of relevant industry experience or equivalent.
• Deep knowledge of SystemVerilog and UVM.
• Experience in developing scalable and portable test-benches.
• Proven experience with verification methodologies and tools such as simulators and waveform viewers.
• Knowledge of scripting languages such as Python, Perl, or TCL.

• Establish DV methodology and develop test plans.
• Create and maintain verification environments, including stimulus and checkers.
• Write tests, debug issues, and ensure coverage and sign-off for RTL freeze and tape-out.
• Develop detailed test and coverage plans based on micro-architecture.
• Track and report DV progress using various metrics, including bugs and coverage.
• Learn to develop block, IP, and SoC level test-benches.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.