The Senior Test Engineer for CMOS Backplane at Google will be part of the Hardware Testing Engineering team, focusing on ensuring the reliability of cutting-edge computing infrastructure. This role involves designing test equipment for prototypes and developing protocols for testing in both production and R&D environments. The engineer will work closely with design engineers to enhance hardware quality and reliability. The position is situated within Raxium, which is pioneering semiconductor materials for next-generation display technologies.

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a specialized field.
• 4 years of experience with Silicon, CMOS, and IC test development.
• 3 years of experience with Silicon test hardware, software debugging, and data analysis in an R&D or manufacturing environment.
• Master's degree or PhD in a related field is preferred.
• Experience with testing software development, Python, and SQL databases.

• Develop, validate, and optimize CMOS Backplane test solutions for microLED display panels.
• Interface with wafer-level probe cards and test equipment to facilitate CMOS testing.
• Identify and resolve electrical issues during wafer-level testing using digital oscilloscopes.
• Collaborate with engineering teams to implement high-speed, automated testing solutions.
• Enhance and develop test frameworks based on requirements from the Reliability Team.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.