As an ASIC Design Verification Engineer at Google, you will be part of a team that develops custom silicon solutions for Google's products. Your role will involve collaborating with hardware architects and design engineers to verify infrastructure IP, interconnects, and memory management systems. You will contribute to building verification components and methodologies that ensure the performance and functionality of Google's SOC offerings. This position emphasizes innovation and the development of high-performance verification environments.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience verifying digital logic at RTL level using SystemVerilog or C/C++.
• Experience creating and using verification components and environments in standard verification methodology such as UVM, SVA, CRV, PSS, or LPDV.
• Experience verifying digital systems using standard IP components/interconnects like microprocessor cores and memory subsystems.
• Experience with scripting languages and software development frameworks.

• Plan and execute the verification of next-generation configurable infrastructure IPs, interconnects, and memory subsystems.
• Create and enhance constrained-random verification environments using SystemVerilog and UVM.
• Identify and write all types of coverage measures for stimulus and corner cases.
• Debug tests with design engineers to deliver functionally correct blocks and subsystems.
• Close coverage measures to identify verification holes and show progress towards tape-out.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.